For undergraduate courses in Advanced Digital Logic and Advanced Digital Design in departments of electrical engineering, computer engineering, and computer science. Introducing the Verilog HDL in a brief format, this text presents a selected set of the changes the popular hardware underwent in its first revision–emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis.
About The Author
Muhammad Saqib
Muhammad Saqib is the founder and lead author of MyCPlus, which he has owned and run since 2004, originally launched during his university years. He holds a Master's degree in Computer Applications and is a Senior Software Engineer with over 15 years of professional experience designing and developing large-scale software and web applications. He has worked for and consulted with major firms including Ford and Hyundai, as well as in the healthcare sector, and currently builds software at a Mobility-as-a-Service (MaaS) transport company. Working hands-on across C/C++, Java, C#/.NET, PHP, and Python, he writes here about C/C++ and Java programming, software development, computer science, and developer tooling.